Clock gating is a wellknown technique to reduce chip dynamic power. Clock gating indian institute of technology kanpur. Clock gating is one of the techniques used to save the dynamic power of clock elements in the design. Pdf a continuous increase in the number of transistors mounted on a single chip brings about the need for. Also it provides the details of parameters which can affect the implementation of the clock gating. Effects of different clock gating techinques on design. Clockgating and its application to low power design of. It ensures power saving by turning on a functional logic block clock, but only when required. The principle behind clock gating is to stop the clock of those sequential elements whose data is not toggling. In a soccpugpu the clock tends to be the longest signal and is being. It also provides the basic clock gating principles, benefits, limitations and enhancements in traditional clock gating scheme. Clock rtl gating is designed into the soc architecture and coded as part.
Clock gating is a popular technique used in many synchronous circuits for reducing dynamic power dissipation, by removing the clock signal when the circuit is not in use. The utilization of the clock pulses, measured by data to clock toggling ratio, left after the employment of synthesis based gating may still be very low. These flipflops use new gating techniques which reduces the power dissipation. Pruning the clock disables portions of the circuitry so that the flipflops in them do not have to switch states. New clockgating techniques for lowpower flipflops acm digital. Clock gating is also often associated with stallability. In sequential circuit one twoinput and gate is inserted in logic for clock gating. Clock gating is one of the most frequently used techniques in rtl to reduce dynamic power consumption without affecting the functionality of the design.
Clock gating for low power circuit design by merge and. Principle of clockgating 9 3 general purpose processor design 3. Latch free clock gating the latchfree clock gating style uses a simple and or or gate depending on the edge on which flipflops are triggered. The work given at 22, discusses the new clock gating techniques for two novel low power flipflops. In soc designs clock gating may be done at two levels. Multicornermultimode support this command uses information from the current scenario only. In sequential circuits clock is the major source of dynamic power consumption. Analysis of clock gating and power gating techniques on. One input to and gate is clock and while the second input is a signal used to control the. Presented circuits overcome the clock dutycycle limitation of previously reported gated flipflops. As lector based clock gating architecture has shown potential in literature, we assumed it to be a better option for sequential logics like counter.
In this paper, we propose avhdlbased technique, to insert clock gating. Latch based clock gating clock gating analysis revisited. And gatingin and gating the simple and gate with enable signal is used to gated the clock with 16bit updown counter as shown in fig 2 567. Low power design is a necessity today in all integrated circuits. In this paper, an activity driven finegrained clock and power gating is proposed. Clock gating is one of useful techniques to reduce the dynamic power consumption of synchronous sequential circuits. Identify portions of the circuit that are currently inactive, retaining their earlier state 3. Two novel low power flipflops are presented in the paper. Clock gating is a very common technique to save power by stopping the clock to a module when the module is not operating.
Power analysis of clock gating at rtl design and reuse. Related work clock gating is a design technique aimed at reducing power dissipation of the sequential elements composing a circuit. In this paper we have focused on the clock gating technique to decrease the. As discussed in clock switching and clock gating checks, there are two kinds of clock gating checks at combinational gates. Rtl clock gating uses this enable signal to control a clock gating circuit which is connected to the.
Glitch free clock gating verilog good clock gating by unknown at friday, march 11, 2016 good clock gating, verilog clock gating, verilog codes, vlsi 3 comments clock gating is a popular technique used in many synchronous circuits for reducing dynamic power dissipation. A power saving techniques used in synchronous circuits i. We also discussed that for an and type check, enable must launch from a negative edgetriggered flipflop and for an or type check, enable must launch. The command cannot introduce setup or hold checks between two nonclock signals. Clock gatingcg, latch free clock gating, latch based clock gating, low power, dynamic power. There are various techniques to reduce dynamic power consumption such as reducing the operating frequency, voltage swing or the capacitive load of the clock. System level, combinational clock gating and sequential clock gating. Clock gating is a technique that enables the saving of electrical power used by computer processors. Similarly, since the offstate of or gate is 1, the enable.
Separate control clock for switching logic, can be any free running clock. Optimization of clock gating logic for low power lsi design core. When the is enable is at low level and the clock is at high level, the clock wont toggle switch because of and gate. Cmos lsi and methods reported in the current literature on minimizing. Power management techniques clock gating vlsi basics. Clock gating works by taking the enable conditions attached to registers, and uses them to gate the clocks. So, employment of a proper clock gating technique is a need of an hour. Clock enabling signals are very well understood at the system level and. The three bits of selection line control all 8 submodule of alu. Reducing switching power with intelligent clock gating. In my last blog, which received huge response, i talked a simple and efficient technique for clock gating. Clock gating was the mainstay of the pentium 4 architectures power saving modes. Low power design techniques basics concepts in chip design.
Here if enable signal goes inactive in between the clock pulse or if it multiple times then gated clock output either can terminate prematurely or generate multiple clock. Pdf power optimization using clock gating and power. The latchfree clock gating style uses a simple and or or gate depending on the edge on which flipflops. Most commonly used methods employed for minimizing. And the reason for those checks was, mainly, to get rid of unacceptable glitches in the en pin. Glitch free clock gating verilog good clock gating. To reduce the power consumption of clock tree, previous work has shown that clock control logic should be synthesized in the highlevel synthesis.
Intelligent clock gating in the design implementation flow wp370 v1. Usually, when applying clock gating techniques, specific conditions should be. In present era every multimedia and dsp based devices will work on some certain clock and as we know, clock signal having great source of power consumption and this is a critical problem in every synchronous circuit. Clock gating is an effective way of reducing the dynamic power dissipation in digital circuits. Clockgating and its application to low power design of sequential circuits i. The methodology was proven in a 200kgate asic, which implemented full scan testing and used rtl clock gating to reduce its power consumption by twothirds. Reduce power in chip designs with sequential clock gating. Identify portions of the circuit that are currently inactive, retaining their earlier state.
In gate based clock gating, any gate is used for clock gating. A processor system composed up of multiple central processing units in a form of a single computing package f or reading. Proposed flipflops use new gating techniques that reduce power dissipation deactivating the clock signal. Leakage power reduction techniques 6 2 clock gating 2. It then uses the covering relationship between the triggering transition of the clock and the active cycles of various flipflops to generate a derived. Lector based clock gating for low power multistage flip. Latch free and clock gating initially many authors suggested using and gate for clock gating because of its simple logic 456. In this way the clock gating technique will reduce the switching activity of clock in order to save the power. The various types of clock gating methodology is used are as follows 1. Pdf implementation of clock gating technique and performing. Dynamic power reduction of synchronous digital design by using of. Clock gating is a common technique for reducing clock power by shutting off the clock to modules by a clock enable signal. The rtl implementation and the power analysis is presented.
But it came with an additional cost of an extra clock gating setup and hold check. It cant arrive anywhere in between the logic high or logic low level of clock signal, but, it needs to meet certain criteria, like if en goes high, it needs to go high before certain time of rising clock edge resulting to setuptime check and needs to remain high for the entire clock cycle high resulting in hold time check. Clock gating applied to the semicustom design of noc routers delivers a power reduction of about 70%. Here if enable signal goes inactive in between the clock pulse or if it multiple times then gated clock output either can terminate prematurely or. In this article, we will discuss the use of clock gating techniques with design examples for achieving lower power and also highlight the impact of clock gating on different areas of the design process like metastability with clock domain crossings and testability. In a typical synchronous circuit such as the general purpose microprocessor, only a. Proposed flipflops use new gating techniques that reduce power dissipation. Clock gating clock gating is a methodology of turning off the clock for a particular block when it is not needed and is used by most soc designs today as an effective technique to save dynamic power. The proposed clock gating technique reduces not only design of an alu with a low power lfsr using clock gating free download. The high en edge may come anytime and may not coincide with a clock edge.
In the waveform of and gating the glitches are seen. In clock gating the gated areas will still be provided with bias power. Figure2 clock gate with latch in system level clock gating a module in a design can be gated when not in use. First, a technique named optimized busspecificclockgating obsc is introduced which reduces the problem of gated flip. Applying a latch free based clock gating technique on this 4bit. In addition, the clock signal tends to be highly loaded. This article discusses the use of clock gating techniques with design examples for achieving lower power and also highlights the impact of clock gating on different areas of the design process like metastability with clock domain crossings and testability. And clock gating technique or latch free clock gating 5. The article also details the dos and donts of clock gating to avoid chip failures and unnecessary power dissipation. The two techniques are coupled in such a way that the clock gating information is used to drive the control signal of powergating circuitry. Clock toggling detection, enabling the mux to change even if one clock is not toggling. Pdf power reduction by clock gating technique researchgate.
Disabling the clock signal clock gating in inactive portions of the chip is a useful. In cadence rtl compiler, this technique is mentioned as none based clock gating and implemented by or gate which is shown in fig. Introduction the sequential circuits in a system are considered major contributors to the power dissipation since one input of sequential circuits is the clock, which is the only signal that switches all the time. To reduce the power consumption of clock tree, previous work has shown that.
As companies, started packing more and more features and applications on the batteryoperated devices mobile handheld laptops, battery backup time became very important. However, note that the clock gating logic will change the clock tree structure, since the clock gating logic will sit in the clock tree. Since, the clock is freerunning, we have to ensure that the change of state of enable signal does not cause the output of the and gate to toggle. And gating in and gating the simple and gate with enable signal is used to gated the clock with 16bit updown counter as shown in fig 2 567. This paper propose a modified clock gating techniques based on acg adaptive clock gating and instruction level clock gating. Clock gating switched off the module which is not active as decided by selection line. Instruction set for the generalpurpose microprocessor 15 3. The technique of clock gating is used to reduce the clock power consumption by cutting off the idle clock cycles. Abstract this paper models the clock behavior in a sequential circuit by a quaternary variable and uses this representation to propose and analyze two clock gating techniques. Clock gating functionally requires only an and or or gate. In the latchfree option we use only one gate and or or but we need to re.
Power reduction by clock gating technique sciencedirect. Performance comparison of various clock gating techniques. Based on clock gating with a quiet period between the two clocks. Therefore it is imperative that a design must contain these enable conditions in order to use and benefit from clock gating. When a mobile is left idle the mobile switches off. In this article, i plan to cover the basic techniques of low power design independent of tools. Clock gating is the power saving technique used for low power design.
Clock gating saves power by pruning the clock tree, at the cost of adding more logic to a circuit. Power optimization using clock gating and power gating multicore sy stem. Generally, key focus on socs is to reduce power consumption in the circuit and the signal which is being used for the longest period of time tend to consume the largest power. Clock gating logic can be added into a design in a variety. The paper also discusses the integration of rtl clock gating with full scan techniques, allowing designs to be both lowpower and fully testable.
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